1. Field of the Invention
This invention relates to the fabrication of metallurgy atop substrates. More particularly, it relates to interconnection systems for metallurgy disposed atop semiconductor devices.
2. Description of the Prior Art
The continuing improvements in semiconductor integrated circuit technology have resulted in the capability of forming increased numbers of transistors, resistors, etc., within a given semiconductor chip. For example, ion implantation has allowed the devices to be smaller, and improved masking and isolation techniques have allowed the devices to be more closely spaced. This miniaturization has resulted in decreased costs and improved performance in integrated circuits. Unfortunately, many of the devices formed within the semiconductor must remain unused in the completed chip because of space required for wiring the circuits together.
For example, a practical state-of-the-art integrated circuit chip, containing between 700 to 2,000 circuits, typically utilizes less than 50 percent of the available circuits. The principal reason for this is the space which the wiring takes up on the surface of the chip. This interconnection metallurgy system atop the chip is extremely complex and the spacing between the wires is very tight. To achieve even a 50 percent efficiency of circuit utilization, at least two or three and possibly four separate levels of complex conductive patterns, each separated by one or more layers of dielectric material, are used.
Ordinarily, the first level conductive pattern on the chip surface interconnects the devices within the chips into circuits and also provides circuit-to-circuit interconnections. The second level conductive pattern conventionally completes the circuit-to-circuit connections and contains a portion of the power buses. The third level may be used for power and I/O connections to a support, such as a module, substrate or card. To interconnect each of these levels of metallization, it is necessary to form feedthrough conductive connections, otherwise known as via studs, within the dielectric layers separating the metallization. The most common technique used today is to etch the dielectric layer atop one level of metallurgy to form feedthrough holes and then deposit the second metallurgy layer over the dielectric layer and into the via holes to contact the first metallurgy layer. However, overetching of one dielectric layer due to mask misalignment, for example, may result in the etching of a lower dielectric layer. It has been necessary to provide increased areas of metallurgy at the via hole sites to prevent the overetching; however, this technique also substantially increases the chip area required for the interconnection metallurgy.
One technique for solving this problem is found in U.S. Pat. No. 3,844,831, issued in the names of E. E. Cass et al, assigned to the same assignee as the present invention. This technique involves the use of dielectric layers with dissimilar etching characteristics, whereby an etchant which attacks one type of dielectric does not substantially affect the other. Although the Cass et al invention has been successful, dielectric etching per se is recognized as causing shorts, pinholes and contamination, no matter how controlled the process.
It would be more desirable to form interconnections between levels of metallurgy without the necessity of etching in the dielectric layers.
One technique for doing so is described in U.S. Pat. No. 4,029,562, issued in the names of B. C. Feng et al, and assigned to the same assignee as the present invention. The Feng et al process involves the depositing of the feedthrough pattern which includes a conventional functional metal and a cap of expendable material atop the conductive film pattern, say the first level of metallization. The expendable material can be removed by an etchant which does not attack the conductive film. The insulator is then deposited atop the first level film as well as the feedthrough pattern by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the insulator. This covers the exposed substrate and thin film surfaces, as well as the expendable material, with the insulator but leaves the side surfaces of the expendable material exposed. The expendable material may then be chemically etched, so as to leave a completely insulated conductive film pattern and exposed feed-throughs so that the second level conductive pattern may be deposited atop the insulator to be interconnected to the first level by the feedthroughs.
Although the Feng et al invention has been successful, it nevertheless involves the prior art process of depositing the feedthrough atop the first level conductor. Because of this process, the feedthrough connections may exhibit poor mechanical strength and/or higher contact resistance, which results in poor manufacturing yields. It would be more desirable to form the via studs as integral parts of the metallurgy so as to eliminate the interface between the studs and the underlying metallurgy.